Semiconductor memory device

ABSTRACT

A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

CLAIM OF PRIORITY

The present application is a continuation of and claims priority to U.S.application Ser. No. 15/782,556, filed Oct. 12, 2017, which is acontinuation of and claims priority to U.S. application Ser. No.15/592,860, now U.S. Pat. No. 10,468,350, filed May 11, 2017, whichclaims priority under 35 U.S.C. § 119 to Korean Patent Application No.10-2016-0100899, filed Aug. 8, 2016 and Korean Patent Application No.10-2016-0136009, filed Oct. 19, 2016 in the Korean Intellectual PropertyOffice, the disclosures of which are hereby incorporated by reference intheir entirety.

BACKGROUND

Embodiments of the present disclosure relate to semiconductor memorydevices, and more specifically, to semiconductor memory devicesincluding air gap-based spacer structures.

Semiconductor devices may be used in the electronics industry because oftheir small size, multi-function, and/or lower manufacturing costs.Semiconductor devices can be classified into semiconductor memorydevices storing logic data, semiconductor logic devices processingoperations of logic data, and hybrid devices having functions of bothmemory devices and logic devices.

Some semiconductor devices may include vertically stacked patterns andcontact plugs electrically connecting the stack patterns to each other.As semiconductor devices have been highly integrated, a distance betweenthe patterns and/or a distance between the patterns and the contactplugs have been reduced. Thus, a parasitic capacitance between thepatterns and/or between the patterns and the contact plugs can increase.The parasitic capacitance can cause performance deterioration (e.g.,reduction of an operating speed) of semiconductor devices.

SUMMARY

Example embodiments of the inventive concepts may provide semiconductordevices with improved electrical characteristics.

According to an example embodiment of the inventive concepts, asemiconductor memory device may include word lines extending in a firstdirection on a semiconductor substrate, bit line structures crossingover the word lines and extending in a second direction intersecting thefirst direction, contact pad structures between the word lines andbetween the bit line structures, in plan view, and a spacer structurebetween the bit line structures and the contact pad structures. Thespacer structure may include a first air gap extending in the seconddirection along sidewalls of the bit line structures and a second airgap surrounding each of the contact pad structures and coupled to thefirst air gap.

According to an example embodiment of the inventive concepts, asemiconductor memory device may include word lines extending in a firstdirection in a semiconductor substrate, bit line structures crossingover the word lines and extending in a second direction intersecting thefirst direction, contact pad structures between the bit line structuresand between the word lines, in plan view, insulating patterns on theword lines and, in plan view, between the contact pad structures andbetween the bit line structures, and a spacer structure between the bitline structures and the contact pad structures. The spacer structure mayinclude a first spacer and a second spacer extending from between thebit line structures and the contact pad structures to between the bitline structures and the insulating patterns, a first air gap between thefirst spacer and the second spacer and extending in the seconddirection, and a second air gap extending from the first air gap tobetween the insulating patterns and the contact pad structures along thefirst direction.

According to an example embodiment of the inventive concepts, asemiconductor memory device may include a first bit line structure and asecond bit line structure extending in a first direction on asemiconductor substrate, wherein the first bit line structure has afirst sidewall and a second bit line structure has a sidewall oppositeto the first sidewall, contact pad structures arranged to be spacedapart from each other in the first direction, between the first andsecond bit line structures, a first spacer structure comprising a firstair gap extending along the first sidewall of the first bit linestructure, a second spacer structure comprising a second air gapextending along the second sidewall of the second bit line structure,and a third spacer structure including a third air gap surrounding thecontact pad structures and coupling the first air gap to the second airgap.

According to some example embodiments of the inventive concepts, asemiconductor memory device may include word lines and adjacent bit linestructures extending in first and second intersecting directions,respectively, on a substrate. Contact pad structures includingrespective conductive landing pads may be provided between respectivesidewalls of the adjacent bit line structures, and may contact impurityregions of the substrate. First air gaps may extend along the respectivesidewalls of the adjacent bitline structures in the second direction andmay separate the respective conductive landing pads therefrom, andsecond air gaps may extend from at least one of the first air gaps andalong multiple sides of the respective conductive landing pads in thefirst direction.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustrating a semiconductor memory deviceaccording to example embodiments.

FIG. 1B illustrates a cross-sectional view taken along lines A-A′ andB-B′ of FIG. 1A.

FIG. 1C illustrates a cross-sectional view taken along lines C-C′ andD-D′ of FIG. 1A.

FIG. 2A is an enlarged view illustrating portion A of FIG. 1A, and FIG.2B is an enlarged view illustrating portion B of FIG. 1B.

FIG. 2C illustrates a semiconductor memory device according to otherexample embodiments and is an enlarged view illustrating portion B ofFIG. 1B.

FIGS. 3A and 3B illustrate a semiconductor memory device according tostill other example embodiments and are enlarged views illustratingportion A of FIG. 1A and portion B of FIG. 1B, respectively.

FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A and 14A are plan viewsillustrating a method of manufacturing a semiconductor memory deviceaccording to example embodiments.

FIGS. 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B and 14B arecross-sectional views taken along lines A-A′ and B-B′ of FIGS. 4A to14A, respectively.

FIGS. 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C and 14C arecross-sectional views taken along lines C-C′ and D-D′ of FIGS. 4A to14A, respectively.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts will now be described more fully hereinafter withreference to the accompanying drawings, in which example embodiments ofthe inventive concepts are shown. This inventive concepts may, however,be embodied in different forms and should not be construed as limited tothe embodiments set forth herein

FIG. 1A is a plan view illustrating a semiconductor memory deviceaccording to example embodiments, FIG. 1B illustrates a cross-sectionalview taken along lines A-A′ and B-B′ of FIG. 1A and FIG. 1C illustratesa cross-sectional view taken along lines C-C′ and D-D′ of FIG. 1A. FIG.2A is an enlarged view illustrating portion A of FIG. 1A, and FIG. 2B isan enlarged view illustration portion B of FIG. 1B. FIG. 2C illustratesa semiconductor memory device according to other example embodiments andis an enlarged view illustrating portion B of FIG. 1B. FIGS. 3A and 3Billustrate a semiconductor memory device according to still otherexample embodiments and are enlarged views illustrating portion A ofFIG. 1A and portion B of FIG. 1B, respectively.

FIGS. 1A, 1B and 1C, a device isolation layer 101 defining activeregions ACT may be disposed in a semiconductor substrate 100. Thesemiconductor substrate 100 may include a silicon substrate, a germaniumsubstrate and/or a silicon-germanium substrate.

In an example, the active regions ACT may have a bar shape and may betwo-dimensionally arranged along a first direction D1 and a seconddirection D2 intersecting or crossing (e.g., perpendicular to) the firstdirection D1. The active regions ACT may be arranged in a zigzag form inplan view and may have a major axis oblique to the first direction D1and the second direction D2.

Word lines WL may be disposed in the semiconductor substrate 100 and mayextend in the first direction D1 in plan view to intersect the activeregions ACT and the device isolation layer 101.

A gate insulating layer 103 may be interposed between the word lines WLand the semiconductor substrate 100. Top surfaces of the word lines WLmay be positioned or extend lower than a top surface of thesemiconductor substrate 100. A gate hard mask pattern 105 may bedisposed on each of the word lines WL.

A first impurity region 1 a and a second impurity region 1 b may bedisposed on each of the active regions ACT at opposite sides of the wordlines WL. Bottom surfaces of the first and second impurity regions 1 aand 1 b may be positioned at a predetermined depth from top surfaces ofthe active regions ACT. The first impurity region 1 a may be disposed ineach of the active regions ACT between the word lines WL. The secondimpurity region 1 b may be spaced apart from the first impurity region 1a to be disposed at end portions of each of the active regions ACT. Thefirst and second impurity regions 1 a and 1 b may include dopants of aconductive type opposite to that of the semiconductor substrate 100.

According to example embodiments, bit line structures BLS may extend inthe second direction D2 to intersect the word lines WL. The bit linestructures BLS may each overlap a plurality of the first impurityregions 1 a. In an example, the bit line structures BLS may each includea polysilicon pattern 121, a silicide pattern 122, a metal pattern 123and a hard mask pattern 125. An insulating interlayer 110 may beinterposed between the semiconductor substrate 100 and the polysiliconpattern 121. A portion of the polysilicon pattern 121 (i.e., a bit linecontact pattern DC) may contact the first impurity regions 1 a. A bottomsurface of the bit line contact pattern DC may be positioned lower thanthe top surface of the semiconductor substrate 100 and higher than thetop surfaces of the word lines WL. In an example, the bit line contactpattern DC may be locally disposed in a recess region 111 formed in thesemiconductor substrate 100 to expose the first impurity region 1 a. Therecess region 111 may have an elliptical shape, and a minimum width ofthe recess region 111 may be greater than a width of each bit linestructure BLS.

A bit line contact spacer DCP may fill the recess region 111 in whichthe bit line contact DC is formed. In some embodiments, the bit contactspacer DCP may extend on or cover opposite sidewalls of the bit linecontact pattern DC. In other embodiments, the bit line contact spacerDCP may surround the bit line contact pattern DC in the recess region111. The bit line contact spacer DCP may be formed of an insulatingmaterial having an etch selectivity with respect to the insulatinginterlayer 110. For example, the bit line contact spacer DCP may includea silicon oxide layer, a silicon nitride layer and/or a siliconoxynitride layer and may be formed of multiple layers. In an example, atop surface of the bit line contact spacer DCP may be positioned at thesame level as a top surface of the insulating interlayer 110.

According to example embodiments, insulating patterns 143 may disposedon the insulating interlayer 110 and may be arranged in the seconddirection D2 between the bit line structures BLS. The insulatingpatterns 143 may overlap with the word lines in plan view and may havetop surfaces at the same level as the top surfaces of the bit linestructures BLS. The insulating patterns 143 may be formed of insulatingmaterial having an etch selectivity with respect to the insulatinginterlayer 110.

According to example embodiments, contact pad structures CPS may bedisposed between the bit line structures BLS to respectively contact thesecond impurity regions 1 b. The contact pad structures CPS may each bedisposed between the word lines WL and between the bit line structuresBLS in plan view. The contact pad structures CPS may each fill a spacedefined (or delimited) by the adjacent bit line structures BLS in thefirst direction D1 and the adjacent insulting patterns 143 in the seconddirection D2.

Top surfaces of the contact pad structures CPS may be positioned higherthan the top surfaces of the bit line structures BLS. A portion of eachof the contact pad structures CPS may overlap with each of the bit linestructures BLS in plan view. In an example, an upper width of eachcontact pad structure CPS may be greater than either a distance betweenthe adjacent bit line structures or a width of each bit line structureBLS.

According to example embodiments, the contact pad structures CPS mayeach include a contact conductive pad 153 contacting each secondimpurity region 1 b, a contact silicide pattern 155 and a landing padLP.

The contact conductive pad 153 may be formed of, for example, a dopedpolysilicon layer and may penetrate the insulating interlayer 110 todirectly contact each second impurity region 1 b. In an example, thecontact conductive pad 153 may be positioned lower than the top surfaceof the semiconductor substrate 100 and higher than the bottom surface ofthe bit line contact pad DC. Furthermore, the contact conductive pad 153may be isolated from the bit line contact pattern DC by the bit linecontact spacer DCP. A top surface of the contact conductive pad 153 maybe positioned lower than a top surface of the metal pattern 123 of eachof the bit line structures BLS.

The contact silicide pattern 155 may extend on or cover the top surfaceof the contact conductive pad 153 and may include, for example, titaniumsilicide, cobalt silicide, nickel silicide, tungsten silicide, platinumsilicide and/or molybdenum silicide. In some embodiments, the contactsilicide pattern 155 may be omitted.

A top surface of the landing pad LP may be positioned higher than thetop surfaces of the bit line structures BLS, and a bottom surface of thelanding pad LP may be positioned lower than the top surfaces of the bitline structures BLS. In an example, the bottom surface of the landingpad LP may be positioned lower than the top surface of the metal pattern123 of each of the bit line structures BLS.

The landing pad LP may be electrically connected to each of the secondimpurity regions 1 b via the contact silicide pattern 155 and thecontact conductive pattern 153. The landing pad LP may include a metalbarrier pattern 157 and a pad metal pattern 159 which are sequentiallystacked.

According to example embodiments, the landing pad LP may include a lowerportion filling between the adjacent bit line structures BLS and betweenthe adjacent insulating patterns 143 and an upper portion extending on aportion of each of the bit line structures BLS. For example, the upperportion of the landing pad LP may partially overlap a portion of each ofthe bit line structures BLS. An upper width of the landing pad LP may begreater than either a distance between the adjacent bit line structuresBLS or a width of each bit line structure BLS. Since the upper portionof the landing pad LP extends on the respective bit line structures BLS,an available surface area of the landing pad LP (e.g., to providecontact with data storage patterns DSP) may be increased. In someembodiments, the actual contact area between the landing pads LP and thedata storage patterns DSP may be smaller than the available surfacearea.

In some embodiments, the upper portion of landing pad LP may have anelliptical shape having a major axis and a minor axis in plan view. Theupper portion of the landing pad LP may have the major axis oblique toboth the first direction D1 and the second direction D2. In someembodiments, the upper portion of landing pad LP may have a roundedrhombus shape, a rounded rectangular shape or a rounded trapezoidalshape.

According to example embodiments, a spacer structure SS may be disposedbetween the bit line structures BLS and the contact pad structures CPS.The spacer structure SS may include a first air gap AG1 extending in thesecond direction D2 along a sidewall of each of the bit line structuresBLS and a second air gap AG2 surrounding a portion of each of thecontact pad structures CPS and having a ring shape in plan view. Thefirst air gap AG1 may be coupled to the second air gap AG2 and may beunder the second air gap AG2.

As an example, the spacer structure SS may further include first andsecond spacers 131 and 135 defining the first air gap AG1 and a thirdspacer 139 defining the second air gap AG2 and surrounding a portion ofeach of the contact pad structures CPS between the bit line structuresBLS.

More specifically, referring to FIGS. 2A and 2B, the first and secondspacers 131 and 135 may extend, on the insulating interlayer 110, in thesecond direction D2 along opposite sidewalls of the bit line structuresBLS. The first and second spacers 131 and 135 may extend in the seconddirection D2 from between the bit line structures BLS and the contactpad structures CPS to between the bit line structures BLS and theinsulating patterns 143. The first and second spacers 131 and 135 mayinclude an insulating material having an etch selectivity with respectto the insulating interlayer 110.

The first spacer 131 may contact the sidewalls of the bit linestructures BLS. The second spacer 135 may be spaced apart from the firstspacer 131 such that the first air gap AG1 may be defined as a gapbetween the first spacer 131 and the second spacer 135. In an example,the first spacer 131 may extend on the sidewalls of the bit line contactpattern DC, and the second spacer 135 may be disposed on the top surfaceof the bit line contact spacer DCP and on the insulating interlayer 110.

According to example embodiments, the second spacer 135 may includefirst portions 135 a adjacent to the contact pad structures CPS andsecond portions 135 b adjacent to the insulating patterns 143. A heightof the first portions 135 a may be smaller than a height of the secondportions 135 b. For example, top surfaces of the first portions 135 amay be positioned lower than top surfaces of the second portions 135 b.The top surfaces of the first portions 135 a may be positioned higherthan the top surface of the contact conductive pattern 153.

The third spacer 139 may surround, on the first portions 135 a of thesecond spacer 135, the lower portion of the landing pad LP. The thirdspacer 139 may have a ring shape in plan view. A portion of the thirdspacer 139 may be positioned below the upper portion of the landing padLP. For example, the portion of the third spacer 139 may overlap withthe upper portion of the landing pad LP in plan view.

More specifically, the third spacer 139 having the ring shape in planview may include a first portion below the landing pad LP and a secondportion between adjacent landing pads LP. A height of the second portionof the third spacer 139 may be smaller than a height of the firstportion of the third spacer 139.

In an example, a portion of the first air gap AG1 and a portion of thesecond air gap AG2 may overlap with the landing pad LP in plan view.

In some embodiments, the second air gap AG2 may be defined as a gapbetween the first spacer 131 and the third spacer 139 and between theinsulating patterns 143 and the third spacer 139. The second air gap AG2may be further defined by a gap between the second spacer 135 and thethird spacer 139. In other embodiments, the second air gap AG2 may bedefined as a gap between the first spacer 131 and the contact padstructures CPS and between the contact pad structures CPS and theinsulating patterns 143, as shown in FIGS. 3A and 3B, such that thethird spacer may be omitted.

More specifically, referring to FIGS. 2A and 2B, the second air gap AG2may have a ring shape similar to the third spacer 139 in plan view andmay surround the lower portion of the landing pad LP. The second air gapAG2 may be coupled to the first air gap AG1 at a space between the bitline structures BLS and the contact pad structures CPS. Furthermore, thesecond air gap AG2 may extend between the insulating patterns 143 andthe contact pad structures CPS from the first air gap AG1, along thefirst direction D1, and along multiple sides of the landing pads LP. Forexample, the first air gap AG1 and the second air gap AG2 may be coupledto (or fluidly communicated with; also referred to herein ascommunicatively coupled to) each other to form a single empty space.Since the second air gap AG2 may extend between the contact padstructures CPS and the insulating patterns 143 along the first directionD1, the second air gap AG2 may couple two adjacent parallel first airgaps AG1 extending in the second direction D2 together. The two adjacentfirst air gaps AG1 and the second air gap AG2 may be coupled to eachother between the adjacent bit line structures BLS to form a singleempty space.

In an example, the first air gap AG1 may have a first width defined as adistance between the first and second spacers 131 and 135, and thesecond air gap AG2 may have a second width defined as a distance betweenthe first spacer 131 and the third spacer 139 (or a distance betweeneach insulating pattern 143 and the third spacer 139). The first widthmay be equal to or greater than the second width.

Furthermore, the first air gap AG1 may include first portions adjacentto the contact pad structures CPS and second portions adjacent to theinsulating patterns 143 (or between the contact pad structures in thesecond direction D2). A height of the first air gap AG1 may be greaterat the second portions than at the first portions.

According to example embodiments, a pad insulating pattern LPI may fillbetween the upper portions of the landing pads LP. The pad insulatingpattern LPI may have a rounded bottom surface. The second air gap AG2may be closed by the bottom surface of the pad insulating pattern LPI. Atop surface of the pad insulating pattern LP1 may be coplanar with thetop surfaces of the landing pads LP.

The pad insulating pattern LPI may include a first capping insulatinglayer 161 and the second capping insulating layer 163 that aresequentially stacked. The first capping insulating layer 161 may have asubstantially uniform thickness, and the second capping insulating layer163 may fill between the landing pads LP. The first capping insulatinglayer 161 may directly contact the landing pads LP and the hard maskpatterns 125 of the bit line structures BLS. Additionally, the firstcapping insulating layer 161 may extend on or cover the top surfaces ofthe insulating patterns 143 and may directly contact the second portions135 b of the second spacer 135 and a portion of the third spacer 139.The first and second capping insulating layer 161 and 163 may include asilicon oxide layer, a silicon nitride layer and/or a silicon oxynitridelayer.

According to example embodiments, data storage patterns DSP mayrespectively be disposed on the contact pad structures CPS. The datastorage patterns DSP may respectively be connected to the secondimpurity regions 1 b via the respective contact pad structures CPS. Thedata storage patterns DSP may each be disposed at a position shiftedfrom a central axis of each of the landing pads LP of the contact padstructures CPS and may contact a portion of each landing pad LP. In anexample, the data storage patterns DSP may be arranged in either ahoneycomb form or a zigzag form in plan view. In some embodiments, thedata storage patterns DSP may overlap with the bit line structures BLS.

In some embodiments, the data storage patterns DSP may each be acapacitor, and may include a lower electrode, an upper electrode and adielectric layer therebetween. In other embodiments, the data storagepatterns DSP may each be a variable resistance pattern capable ofswitching between two resistance states by an electrical pulse appliedto a memory element. For example, the data storage pattern DSP mayinclude a phase change material capable of changing a crystalline stateaccording to an amount of electrical current, such as perovskitecompounds, transition metal oxide, magnetic materials, ferromagneticmaterials or antiferromagnetic materials.

According to an example embodiment as shown in FIG. 2C, in the memorydevice as described with reference to FIGS. 1A, 1B and 1C, the first airgap AG1 may vertically extend along the sidewalls of the bit linecontact pattern DC.

According to an example embodiment as shown in FIGS. 3A and 3B, in thememory device as described with reference to FIGS. 1A, 1B and 1C, thethird spacer 139 may be omitted. Thus, the second air gap AG2 may beprovided between the first spacer 131 and the pad structures CPS andbetween the insulating patterns 143 and the contact pad structures CPS.

FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A and 14A are plan viewsillustrating a method of manufacturing a semiconductor memory deviceaccording to example embodiments. FIGS. 4B, 5B, 6B, 7B, 8B, 9B, 10B,11B, 12B, 13B and 14B are cross-sectional views taken along lines A-A′and B-B′ of FIGS. 4A to 14A, respectively. FIGS. 4C, 5C, 6C, 7C, 8C, 9C,10C, 11C, 12C, 13C and 14C are cross-sectional views taken along linesC-C′ and D-D′ of FIGS. 4A to 14A, respectively.

Referring to FIGS. 4A, 4B and 4C, a device isolation layer 101 definingactive regions ACT may be formed in a semiconductor substrate 100. In anexample, the active regions ACT have a bar shape and may be arranged intwo dimensions in a first direction D1 and a second direction D2intersecting or crossing (e.g., perpendicular to) the first directionD1. The active regions ACT may be arranged in a zigzag form in plan viewand may have a major axis oblique to both the first direction D1 and thesecond direction D2.

A plurality of word lines WL may be disposed on the semiconductorsubstrate 100 to extend in the direction D1. In an example, the activeregions ACT and the device isolation layer 101 may be patterned to formgate recess regions 102 extending in the first direction D1, and afterforming gate insulating layers in the gate recess regions 102,respectively, the word lines WL may be respectively formed on the gateinsulating layers in the respective gate recess regions 102. Bottomsurfaces of the gate recess regions 102 may be positioned higher than abottom surface of the device isolation layer 101. Top surfaces of theword lines WL may be positioned lower than a top surface of the deviceisolation layer 101. Gate hard mask patterns 105 may be respectivelyformed in the gate recess regions 102 in which the word lines WL areformed.

After forming the word lines WL, first and second impurity regions 1 aand 1 b may be respectively formed in the active regions ACT at oppositesides of the word lines WL. The first and second impurity regions 1 aand 1 b may be formed by an ion implantation process and may includedopants of a conductivity type opposite to that of the active regionsACT.

An insulating interlayer 110 may be formed on the semiconductorsubstrate 100. The insulating interlayer 110 may be formed of either asingle insulating layer or a plurality of insulating layers. Theinsulating interlayer 110 may include, for example, a silicon oxidelayer, a silicon nitride layer and/or a silicon oxynitride layer.

According to example embodiments, the semiconductor substrate 100 andthe insulating interlayer 110 may be patterned to form recess regions111 respectively exposing the first impurity regions 1 a. In an example,the recess regions 111 may have an elliptical shape having a major axisin the second direction D2. Additionally, the recess regions 111 may bearranged in either a honeycomb form or a zigzag form in plan view.

In some embodiments, the recess regions 111 may be formed by ananisotropic etching process. In this case, a portion of the deviceisolation layer 101 and a portion of each of the gate hard mask patterns105 that are adjacent to the first impurity regions 1 a may be etchedtogether. Bottom surfaces of the recess regions 111 may be positionedhigher than bottom surfaces of the first impurity regions 1 a, and aportion of the device isolation layer 101 and a portion of each of thegate hard mask patterns 105 may be exposed by the recess regions 111.

Referring to FIGS. 5A, 5B and 5C, bit line structures BLS may be formedon the insulating interlayer 110 having the recess regions 111 and mayextend in the second direction D2.

The formation of the bit line structures BLS may include forming a firstconductive layer on the insulating interlayer 110 to fill the recessregions 111, forming a second conductive layer on the first conductivelayer, forming a hard mask layer on the second conductive layer, forminga bit line mask pattern on the hard mask layer, and sequentially etchingthe hard mask layer, the second conductive layer and the firstconductive layer using the bit line mask pattern as an etch mask. Thebit line mask pattern may be removed after etching the hard mask layer,the second conductive layer and the first conductive layer. Here, thefirst conductive layer may be formed of a doped semiconductor layer(e.g., a doped polysilicon layer), and the second conductive layer maybe formed of a metal layer such as a tungsten layer, an aluminium layer,a titanium layer or a tantalum layer. Furthermore, a metal silicidelayer may be formed between the first conductive layer and the secondconductive layer.

Thus, the bit line structures BLS may each include a polysilicon pattern121, a silicide pattern 122, a metal pattern 123 and a hard mask pattern125 that are sequentially stacked. Here, a portion of the polysiliconpattern 121 may be locally formed in the recess regions 111 to form abit line contact pattern DC that directly contacts the first impurityregion 1 a. Additionally, sidewalls of the polysilicon pattern 121 maybe spaced apart from sidewalls of the respective recess regions 111.

Referring to FIGS. 6A, 6B and 6C, a first spacer 131 and a firstsacrificial spacer 133 may be formed on opposite sidewalls of each ofthe bit line structures BLS.

More specifically, the formation of the first spacer 131 may includedepositing a spacer layer that fills the recess regions 111 andconformally covers the bit line structures BLS and anisotropicallyetching the spacer layer. Here, the spacer layer may include a firstnitride layer, an oxide layer and a second nitride layer that aresequentially stacked. When anisotropically etching the spacer layer(i.e., the second nitride layer), the oxide layer may be used as an etchstop layer, and the oxide layer and the second nitride layer may locallyremain in the recess regions 111 to form a bit line contact spacer DCP.The first nitride layer may remain the recess regions 111 and theopposite sidewalls of the respective bit line structures BLS to form thefirst spacer 131. The first spacer 131 may include a lower portionformed in the recess regions 111 and an upper portion covering theopposite sidewalls of the respective bit line structures BLS. The lowerportion of the first spacer 131 may form the bit line contact spacerDCP. The first spacer 131 may extend in the second direction D2 alongthe opposite sidewalls of the respective bit line structures BLS. Insome embodiments, the first spacer 131 may fill the recess regions 111and extend along the opposite sidewalls of the respective bit linestructures BLS.

After forming the first spacer 131, a first sacrificial layer may beformed to conformally extend on or cover a part of or an entire surfaceof the resulting structure, and the first sacrificial layer may beanisotropically etched to form the first sacrificial spacer 133 on theopposite sidewalls of the respective bit line structures BLS accordingto some embodiments. The first sacrificial spacer 133 may be formed ofan insulating material having an etch selectivity with respect to thefirst spacer 131, for example, silicon oxide. The first sacrificialspacer 133 may be disposed on the first spacer 131 and may extend in thesecond direction D2 along the opposite sidewalls of the respective bitline structures BLS.

After forming the first sacrificial spacer 133, a second spacer layer134 may be formed to conformally extend on or cover the bit linestructures BLS, the first sacrificial spacer 133 and the insulatinginterlayer 110. The second spacer layer 134 may be formed of aninsulating material having an etch selectivity with respect to both thefirst sacrificial spacer 133 and the insulating interlayer 110. Thesecond spacer layer 134 may be formed of, for example, a silicon nitridelayer and/or a silicon oxynitride layer.

Referring to FIGS. 7A, 7B and 7C, sacrificial patterns 141 andinsulating pattern 143 may be formed to be alternately arranged alongthe second direction D2 between the bit line structures BLS. Forexample, the insulating patterns 143 may be formed on the word lines WL,respectively, and the sacrificial patterns 141 may be formed on thesecond impurity regions 1 b, respectively.

In an example, the formation of the sacrificial patterns 141 and theinsulating patterns 143 may include forming a sacrificial layer on thesecond spacer layer 134 to fill between the bit line structures BLS,forming, on the sacrificial layer, mask patterns extending parallel tothe word lines WL in the first direction D1, anisotropically etching thesacrificial layer using the mask patterns and the bit line structuresBLS as an etch mask to form the sacrificial patterns 141 exposing thesecond spacer layer 134 on the word lines WL, forming the insulatinglayer filling between the sacrificial patterns 141 and between the bitline structures BLS, and planarizing the insulating layer to expose topsurfaces of the mask patterns.

In plan view, the sacrificial patterns 141 may be spaced apart from eachother in the second direction D2 and may be disposed between the wordlines WL. The sacrificial patterns 141 may be formed of a materialhaving an etch selectivity with respect to the second spacer layer 134.For example, the sacrificial patterns 141 may be formed of aspin-on-hard mask (SOH) material (e.g., SOH silicon oxide). When formingthe sacrificial patterns 141, upper surfaces of the bit line structuresBLS between the mask patterns may be partially etched.

The insulating patterns 143 may fill a space defined by the bit linestructures BLS and the sacrificial patterns 141 and may overlap with theword lines WL in plan view. The insulating patterns 143 may be formed ofan insulating material having an etch selectivity with respect to thesacrificial patterns 141. For example, the insulating patterns 143 maybe formed of silicon oxide, silicon nitride and/or silicon oxynitride.

Referring to FIGS. 8A, 8B and 8C, after forming the insulating patterns143, the sacrificial patterns 141 may be removed using an etch recipehaving an etch selectivity with respect to the insulating patterns 143and the second spacer layer 134. Thus, a contact region may be definedby the bit line structures BLS and the insulating patterns 143, and aportion of the second spacer layer 134 may be exposed.

Subsequently, the portion of the second spacer layer 134 exposed by thecontact region, a portion of the insulating interlayer 110 and a portionof the semiconductor substrate 100, a portion of the device isolationlayer 101 may be anisotropically etched using the insulating patterns143 and the bit line structures BLS as an etch mask to form contactholes 145 exposing the second impurity regions 1 b, respectively. As thecontact holes 145 are formed, a second spacer 135 may be formed on theopposite sidewalls of the respective bit line structures BLS.

As the portion of the semiconductor substrate 100 and the portion of thedevice isolation layer 101 are etched when forming the contact holes145, bottom surfaces of the contact holes 145 may be positioned lowerthan a top surface of the semiconductor substrate 100. The contact holes145 may expose a portion of the bit line contact spacer DCP in therecess regions 111.

Referring to FIGS. 9A, 9B and 9C, preliminary contact patterns 151 maybe formed in the contact holes 145, respectively. The preliminarycontact patterns 151 may each be formed to fill a portion of each of thecontact holes 145. In an example, top surfaces of the preliminarycontact patterns 151 may be positioned lower than top surfaces of thehard mask patterns 125 of the bit line structures BLS.

The formation of the preliminary contact patterns 151 may includedepositing a conductive layer to fill the contact holes 145, planarizingthe conductive layer to expose top surfaces of the bit line structuresBLS and the insulating patterns 143, and recessing a top surface of theconductive layer. As a result, the preliminary contact patterns 151 areformed to expose an upper portion of the second spacer 135 to thecontact holes 145.

The preliminary contact patterns 151 may include, for example, a dopedsemiconductor material (e.g., doped silicon), metal (e.g., tungsten,aluminium, titanium and/or tantalum), conductive metal nitride (e.g.,titanium nitride, tantalum nitride, and/or tungsten nitride) and/ormetal-semiconductor alloy (e.g., metal silicide).

In some embodiments, while forming the preliminary contact patterns 151,the top surfaces of the insulating patterns 143 and the bit linestructures BLS may be recessed, and thus top surfaces of the firstsacrificial spacer 133 and the first and second spacers 131 and 135 maybe exposed.

Referring to FIGS. 10A, 10B and 10C, after forming the preliminarycontact patterns 151, the upper portion of the second spacer 135 exposedby the contact holes 145 and an upper portion of the first sacrificialspacer 133 are may be etched. For example, the second spacer 135 exposedby the contact hole 145 and the first sacrificial spacer 133 may beetched by either an anisotropic etch process or an isotropic etchprocess. A top surface of the etched first sacrificial spacer 133 and atop surface of the etched second spacer 135 may be positioned atsubstantially the same level. As the first sacrificial spacer 133 andthe second spacer 135 are etched, an upper width of each of the contactholes 145 that are not filled by the preliminary contact patterns 151may be increased. Furthermore, while etching the upper portions of thesecond spacer 135 and the first sacrificial spacer 133, a portion of thehard mask pattern 125 of each of the bit line structures BLS may beetched together, thereby reducing an upper width of the hard maskpattern 125. As result, the first sacrificial spacer 133 and the secondspacer 135 may respectively include first portions 133 a and 135 abetween the preliminary contact patterns 151 and the bit line structuresBLS and second portions 133 b and 135 b between the insulating patterns143 and the bit line structures BLS. Top surfaces of the first portions133 a and 135 a may be positioned lower than those of the secondportions 133 b and 135 b. For example, the first portions 133 a and 135a may have a lower height than the second portions 133 b and 135 b.

Referring to FIGS. 11A, 11B and 11C, a second sacrificial spacer 137having a ring shape in plan view may be formed in the contact holes 145.

The formation of the second sacrificial spacer 137 may include forming asecond sacrificial spacer layer that conformally covers inner surfacesof upper portions of the contact holes 145, and anistropically etching(e.g., etching-back) the second sacrificial spacer layer to expose thetop surfaces of the preliminary contact patterns 151. The secondsacrificial spacer 137 may be disposed on the first portions 133 a and135 a of the first sacrificial spacer 133 and the second spacer 135 andmay conformally extend on or cover the first spacer 131 and portions ofsidewalls of the insulating patterns 143. In some embodiments, athickness of the second sacrificial spacer 137 may be equal to or lessthan that of the first sacrificial spacer 133. The second sacrificialspacer 137 may directly contact a top surface of the first sacrificialspacer 133 (e.g., top surfaces of the first portions 133 a).Furthermore, the second sacrificial spacer 137 may directly contact twoadjacent first sacrificial spacers 133 in the respective contact holes145. The second sacrificial spacer 137 may be formed of the samematerial as the first sacrificial spacer 133 and may be formed of amaterial having an etch selectivity relative to the first and secondspacers 131 and 135.

Referring to FIGS. 12A, 12B and 12C, a third spacer 139 may be formed onthe second sacrificial spacer 137. The third spacer 139 may be formed byconformally forming a third spacer layer in the contact holes 145 inwhich the second sacrificial spacer 137 are formed and then etching backthe third spacer layer. The third spacer 139 may be formed on thepreliminary contact patterns 151 and the first portions 133 a and 135 aof the first sacrificial spacer 133 and the second spacer 135. The thirdspacer 139 may be formed of a material having an etch selectivityrelative to the second sacrificial spacer 137 and may be thicker thanthe second sacrificial spacer 137.

After forming the third spacer 139, the top surfaces of the preliminarycontact patterns 151 exposed by the third spacer 139 may be recessed toform contact conductive patterns 153. In an example, top surfaces of thecontact conductive patterns 153 may be positioned lower than the topsurfaces of the metal patterns 123 of the bit line structures BLS. Thus,portions of sidewalls of the first portions 135 a of the second spacer135 and portions of the sidewalls of the insulating patterns 143 may beexposed by the contact holes 145.

Referring to FIGS. 13A, 13B and 13C, contact silicide patterns 155 maybe formed on the top surfaces of the contact conductive patterns 153exposed by the second sacrificial spacer 137 and the third spacer 139.The contact silicide patterns 155 may be formed by reacting the topsurfaces of the contact conductive patterns 153 with a metal material.The contact silicide patterns 155 may be formed of, for example,titanium silicide, cobalt silicide, nickel silicide, tungsten silicide,platinum silicide and/or molybdenum silicide. In some embodiments, theformation of the contact silicide patterns 155 may be omitted.

Subsequently, landing pads LP may be formed to fill the contact holes145 in which the second sacrificial spacer 137 and the third spacer 139are formed and to be connected to the contact conductive patterns 153,respectively.

The formation of the landing pads LP may include conformally depositinga barrier metal layer 157 on some portions of or the entire surface ofthe semiconductor substrate 100, forming a metal layer 159 on thebarrier metal layer 157 to fill the contact holes 145, forming maskpatterns MP on the metal layer 159, and forming a pad recess region RRby sequentially etching the metal layer 159 and the metal barrier layer157 using the mask patterns MP as an etch mask. Here, the metal layer159 may be fully fill the contact holes 145 and may partially orentirely extend on or cover the bit line structures BLS.

The pad recess region RR may separate the landing pads LP form eachother and may have a bottom surface lower than the surfaces of the bitline structures BLS. Furthermore, while forming the pad recess regionRR, a portion of the hard mask pattern 125, a portion of the secondsacrificial spacer 137 and a portion of the third spacer 139 may beetched. Thus, a portion of the second sacrificial spacer 137 may beexposed by the pad recess region RR between the landing pads LP. Thefirst portion 133 a of the first sacrificial spacer 133 adjacent to thecontact pad structures CPS may overlap with upper portions of thelanding pads LP, and thus may not be exposed by the pad recess regionRR.

The landing pads LP may each include a lower portion filling a lowerportion of each of the contact holes 145 and an upper portion extendingto the top surface of each of the bit line structures BLS. The upperportion of each of the landing pads LP may have an elliptical shape inplan view and may have a major axis oblique to both the first and seconddirections D1 and D2. Although a width of each of the landing pads LP ina direction of the major axis is increased while forming the landingpads LP, since the landing pads LP each have the major axis oblique toboth the first and second directions D1 and D2, a process margin betweenthe landing pads LP may be secured.

Referring to FIGS. 14A, 14B and 14C, after forming the pad recessregions RR, the first and second sacrificial spacers 133 and 137 may beremoved to form a first air gap AG1 and a second air gap AG2. The firstand second air gaps AG1 and AG2 may be formed by performing an isotropicetch process using an etch recipe with an etch selectivity relative tothe first through third spacers 131, 135 and 139 and the insulatingpatterns 143.

As an example, the first and second air gaps AG1 and AG2 may be formedby etching the first and second sacrificial spacers 133 and 137 with anetchant provided through the pad recess region RR. For example, theetchant may be provided to a portion of the second sacrificial spacer137 and the second portions 133 b of the first sacrificial spacer 133that are exposed by the pad recess region RR. Since the portion of thesecond sacrificial spacer 137 has a ring shape in plan view and directlycontacts the first portions 133 a of the first sacrificial spacer 133,although the first portions 133 a of first sacrificial spacer 133 areexposed by the pad recess regions RR, an wet etchant may be provided tothe first portions 133 a of the first sacrificial spacer 133 through anempty space that is formed by removing the second sacrificial spacer137. For example, portions of the first sacrificial spacer 133 (i.e.,the first portions 133 a adjacent to the contact pad structures CPS) maybe removed through the empty space formed by removing the secondsacrificial spacer 137 formed in the ring shape as well as through anempty space formed by removing the second portions 133 b of the firstsacrificial spacer 133.

As the first and second sacrificial spacers 133 and 137 are removed, thefirst air gap AG1 defined as a gap between the first and second spacers13 land 135 (i.e., an empty space formed by the removal of the firstsacrificial spacer 133) and the second air gap AG2 may be defined as agap between the first spacer 131 and the third spacer 139 and betweenthe insulating patterns 143 and the third spacer 139 (i.e., an emptyspace formed by the removal of the second sacrificial spacer 137). Here,the first air gap AG1 and the second air gap AG2 may be coupled (or influid communication) together to form a single empty space. Furthermore,since the second sacrificial spacer 137 directly contacts, in therespective contact holes 145, the first sacrificial spacers 133 adjacentto each other in the first direction D1 and extending in the seconddirection D2, the second air gap AG2 may be coupled to two first airgaps AG1 extending in the second direction D2.

Next, after forming the first and second air gaps AG1 and AG2, as shownin FIGS. 1A, 1B and 1C, a first capping insulating layer 161 conformallycovering an inner surface of the pad recess region RR and a secondcapping insulating layer 163 fully filling the pad recess region RR maybe sequentially formed.

The first capping insulating layer 161 may be formed using a depositionprocess having poor step coverage, and thus may seal the second air gapAG2 while not filling the second air gap AG2.

According to example embodiments, the first sacrificial spacer extendingalong the sidewalls of the bit line structures and the secondsacrificial spacer surrounding the lower portion of the landing pad anddirectly contacting the first sacrificial spacer may be formed. Thus,when forming the air gap between the bit line structures and the contactpad structures, the first sacrificial spacer covered by the landing padmay be easily removed. As a result, since the air gap is formed toextend along the sidewalls of the bit line structures and surround thelower portion of the landing pad, a parasitic capacitance between thebit line structures and the contact pad structures can be reduced.Therefore, reliability and electrical properties of the semiconductormemory device can be improved.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the inventive concepts. Thus, to themaximum extent allowed by law, the scope is to be determined by thebroadest permissible interpretation of the following claims and theirequivalents, and shall not be restricted or limited by the foregoingdetailed description.

What is claimed is:
 1. A semiconductor memory device, comprising: wordlines extending in a first direction in a semiconductor substrate; a bitline contact pattern; bit line structures on the bit line contactpattern, the bit line structures crossing over the word lines andextending in a second direction intersecting the first direction; bitline spacer structures on sidewalls of the bit line structures; contactconductive pads arranged in a row between the bit line structures inplan view; and insulating patterns between the contact conductive padsand between the bit line structures, wherein top surfaces of the wordlines are lower than a top surface of the semiconductor substrate,wherein a bottom surface of the bit line contact pattern is lower thanthe top surface of the semiconductor substrate, wherein a bottom surfaceof the contact conductive pad is lower than the top surface of thesemiconductor substrate and is higher than the bottom surface of the bitline contact pattern, wherein each of the bit line structures comprisesa polysilicon pattern, a silicide pattern, a metal pattern, and a hardmask pattern, and wherein each of the bit line spacer structurescomprises: a first spacer directly on the sidewalls of the bit linestructures and extending along the bit line structures in the seconddirection; a second spacer extending parallel with the first spacer inthe second direction, the second spacer having a topmost surface lowerthan a topmost surface of the first spacer and higher than a topmostsurface of the metal pattern of the bit line structure; a first air gapbetween the first spacer and the second spacer extending in the seconddirection; a third spacer above the second spacer; and a second air gapextending from the first air gap to between the first spacer and thethird spacer.
 2. The device of claim 1, wherein the first air gaps ofthe bit line spacer structures are parallel to each other.
 3. The deviceof claim 1, wherein the first air gap comprises first portions adjacentto the contact conductive pads and second portions adjacent to theinsulating patterns, and wherein a height of the first air gap isgreater at the second portions than at the first portions.
 4. The deviceof claim 1, wherein the first air gap has a first width and the secondair gap has a second width smaller than the first width.
 5. The deviceof claim 1, further comprising a landing pad connected to a respectiveone of the contact conductive pads, wherein an upper portion of thelanding pad partially overlaps with a portion of a respective one of thebit line structures, and wherein an upper width of the landing pad isgreater than a distance between adjacent ones of the bit linestructures.
 6. The device of claim 5, wherein the first air gap includesfirst portions adjacent to the contact conductive pads and secondportions adjacent to the insulating patterns, and wherein the firstportion of the first air gap and a portion of the second air gap overlapwith the landing pad in plan view.
 7. The device of claim 1, wherein thethird spacer has a ring shape surrounding a respective one of thecontact conductive pads in a plan view.
 8. The device of claim 7,wherein the second air gap couples two adjacent ones of the first airgaps.
 9. A semiconductor memory device, comprising: word lines extendingin a first direction in a semiconductor substrate; bit line structurescrossing over the word lines and extending in a second directionintersecting the first direction, each of the bit line structurescomprising a polysilicon pattern, a silicide pattern, a metal pattern,and a hard mask pattern; bit line spacer structures on sidewalls of thebit line structures; contact conductive pads arranged in a row betweenthe bit line structures in plan view; and insulating patterns betweenthe contact conductive pads and between the bit line structures; andwherein each of the bit line spacer structures comprises: a first spacerdirectly on the sidewalls of the bit line structures and extending alongthe bit line structures in the second direction; a second spacerextending parallel with the first spacer in the second direction, athird spacer above the second spacer; and a first air gap between thefirst spacer and the second spacer extending in the second direction,wherein a topmost surface of the second spacer is lower than a topmostsurface of the first spacer and higher than a topmost surface of themetal pattern of the bit line structure.
 10. The device of claim 9,wherein each of the bit line spacer structures further comprises asecond air gap extending from the first air gap to between the firstspacer and the third spacer.
 11. The device of claim 10, wherein thesecond air gap surrounds a respective one of the contact conductive padsin plan view.
 12. The device of claim 10, wherein the first air gap hasa first width and the second air gap has a second width smaller than thefirst width.
 13. The device of claim 9, wherein the first air gapcomprises first portions adjacent to the contact conductive pads andsecond portions adjacent to the insulating patterns, and wherein aheight of the first air gap is greater at the second portions than atthe first portions.
 14. The device of claim 9, further comprising alanding pad connected to a respective one of the contact conductivepads, wherein an upper portion of the landing pad partially overlapswith a portion of a respective one of the bit line structures, andwherein an upper width of the landing pad is greater than a distancebetween adjacent ones of the bit line structures.
 15. The device ofclaim 9, wherein the third spacer has a ring shape surrounding arespective one of the contact conductive pads in a plan view.
 16. Thedevice of claim 9, wherein the first air gap continuously extends alongthe sidewalls of the bit line structures.